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Description

The V6065 is a next-generation heterogeneous embedded computing module in a 3U VPX form factor, built around the AMD / Xilinx® Versal® Premium Adaptive System-on-Chip (ASoC). It features ruggedized high-speed optical and electrical I/O, an XMC site, and SOSA™-aligned profile options. The module supports either the Versal® Premium VP1502 or VP1702 devices.

Within a single 3U VPX card, the V6065 integrates three 100G optical interfaces (300G total bandwidth), a large FPGA fabric, embedded ARM processor cores, and an XMC expansion site. This makes it well suited for high-bandwidth interface applications where data is locally processed or pre-processed before being distributed over the VPX backplane or optical links.

Typical use cases include sensor interfacing, data processing and distribution, FPGA co-processing, and protocol bridging. Applications such as radar, signals intelligence, electronic warfare, video processing, storage, medical imaging, and embedded communications systems can all benefit from the capabilities of the V6065.

By leveraging the Versal® hard silicon features—such as integrated Ethernet interfaces, PCIe controllers, DMA engines, and associated AMD / Xilinx® software drivers—the V6065 enables a robust ecosystem for high-performance Ethernet applications. Beyond Ethernet, the FPGA fabric can host New Wave DV IP cores supporting protocols including Fibre Channel, ARINC-818, sFPDP, Aurora, and others, making the module ideal for systems requiring mixed protocols or protocol conversion.

The V6065 can operate as a standalone data interface and processing solution within a single 3U VPX module. It offers twelve (12) full-duplex optical ports supporting data rates from 1G to 25G per lane, along with extensive FPGA resources, ARM processor cores, and an XMC site. It can also be deployed alongside CPUs and/or GPUs in a 3U VPX system, offloading data interface tasks so those processors can focus on high-value applications and algorithms, with data delivered directly over the backplane.

The inclusion of an XMC site provides additional flexibility and customization to meet specific application requirements, such as multi-level security or secure boot. This architecture also supports long-term scalability.

Specifications

NETWORK INTERFACE
Up to twelve (12) 1G to 25G optical ports (front & backplane options)
• 850nm multi-mode optics
22 lanes of electrical high-speed network I/O available to the backplane
OPTIONAL ADDITONAL PROTOCOLS
Ethernet, Fibre Channel, sFPDP, ARINC 818, Aurora
ASoC (FPGA)DEVICE
AMD / Xilinx® Versal® VP1502, VP1702
MEMORY
3 banks of 16GB (48GB total) up to 1866MHz/3733 Mbps LPDDR4 SDRAM
THERMAL SENSORS
2 digital temperature sensors
COMPLIANCE
VITA 20, 42, 47, 48.2, 65, 66.5
PHYSICAL CHARACTERISTICS
Dimensions
170.75mm length: Face of carrier to back edge of Guide pin connectors
189.22mm length: MPO flip door to back edge of Guide pin connectors 100mm width: Edge of guide rail to guide rail
24.64mm height: From primary cover to secondary cover
Weight
<1.764 lbs (800g)
POWER CHARACTERISTICS
Power Draw (Max)
216W
Cooling Capability in 48.2 ECC4 C2 (85° C): 150W Power Supply: 12V
Power Supply
12V
TEMPERATURE
Operating
-40˚ C to 85˚ C (conduction-cooled)
Storage
-55˚ C to 105˚ C

Resources & documentation

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