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Présentation

40 bidirectional digital I/O channels in VITA 93 format

Within the Acromag embedded processor, FPGA and I/O portfolio, the QMC470 provides 40 general-purpose bidirectional digital I/O points in a compact 26 × 78.25 mm VITA 93 mezzanine.

Inputs are TTL compatible, while outputs use a CMOS open-drain configuration.

With up to 15 mA sink capability, the outputs can interface directly with compatible digital devices and standard relay racks.

Programmable interrupts, debounce and output readback

Every channel supports programmable event detection for:

  • change of state;
  • low-to-high transitions;
  • high-to-low transitions.

Programmable debounce helps reject false events caused by noise or switching transients.

Output readback registers allow the host to verify output state without allocating additional input channels.

At power-up or system reset, outputs enter a failsafe state to prevent unintended momentary switching.

TTL inputs and CMOS open-drain outputs

Input signals cover -0.25 V to +5.25 V DC, with a typical threshold of 1.5 V.

The open-drain outputs provide up to 15 mA DC sink current and include onboard 4.7 kΩ pull-up resistors.

Each channel also incorporates electronic overvoltage protection.

The QMC470 therefore combines digital monitoring and control in a single compact module for industrial applications, test systems and embedded computers requiring high I/O density.

PCIe with air- and conduction-cooled versions

The carrier interface is PCI Express 2.1 Gen1 x1 at 2.5 Gbps.

Two versions are available:

  • QMC471-1111 - air cooled, 0 to +70°C at 200 LFM.
  • QMC472-1111 - conduction cooled, -40 to +85°C.

The USW-API software environment supports Windows, Linux and VxWorks.

The VITA 93 format allows the module to be integrated through suitable carriers into PCIe, VPX, CompactPCI, VNX+ and other embedded platforms.

Versions

Part number Configuration Cooling
QMC471-1111 40 TTL/CMOS digital I/O channels Air
QMC472-1111 40 TTL/CMOS digital I/O channels Conduction

Specifications

DIGITAL INPUTS
Input channel configuration
40 buffered inputs with programmable debounce circuitry
Input signal voltage range
-0.25V to +5.25V DC
Input low voltage range
0.8V max to 0.25V below common ground
Input high voltage range
2.2V min to 0.25V above +5V supply max
Input threshold
1.5V typical
Input transition rise or fall time
5.5ns maximum
Input response time
1.5ns typical
DIGITAL OUPUTS
Output channel configuration
40 open-drain CMOS outputs
Output low voltage range
0.1V DC typical, 0.4V DC maximum at 12mA
Output high voltage range
4.8V DC at -10μA
Output “ON” current range
0 to 15mA DC (for V ≤ 0.5V)
Output RDS ON resistance
12.5Ω maximum (25°C)
Output pull-ups
4.7kΩ integrated pull-ups installed on board
PCI EXPRESS BASE SPECIFICATION - Conforms to revision 2.1
Lanes
1 lane in each direction
Bus Speed
2.5 Gbps (Generation 1)
Memory
256k space: Base address register 0
1M space: Base address register 2
ENVIRONMENTAL
Operating temperature range
Air-cooled: 0 to 70°C (200 LFM airflow)
Conduction-cooled: -40°C to +85°C
Storage temperature
-55 to 125°C
Relative humidity
5 to 95% non-condensing
Power
+3.3 VDC (±5%): 0.40 A typical
+3.3 VDC AUX (±5%): 0.10 A typical
+12 VDC (±5%): Not used
MTBF (Mean Time Between Failure)
Contact factory
PHYSICAL
Size
Length: 78.25mm (3.08 in)
Width: 26.00mm (1.02 in)
Height: 11.00mm (0.43 in)
Weight
Unit weight: 8.9g (0.31 oz)

Resources & documentation

Bring 40 monitoring and control signals into one compact QMC module

Bring 40 monitoring and control signals into one compact QMC module

With 40 bidirectional TTL/CMOS I/O channels, programmable interrupts, output readback and failsafe operation, the QMC470 delivers high-density digital control in a compact VITA 93 footprint.

ECRIN Systems can define the complete implementation around the module: electrical levels, input/output requirements, QMC carrier, cooling and combination with isolated or analog QMC functions.

Need to consolidate a large number of TTL I/O signals in your embedded computer? Send us your requirements to define the appropriate QMC and carrier configuration.

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